`include "defines.v"

module mem_wb(
    input  wire                      clock,
	input  wire                      reset,
	
	input  wire[`RegisterAddressBus] mem_wd,
	input  wire                      mem_wreg,
	input  wire[`RegisterBus]        mem_wdata,
	
	input wire[`RegisterBus]         mem_hi,
	input wire[`RegisterBus]         mem_lo,
	input wire						 mem_hilo_we,

	input wire[`STALL_BUS]           stall,

	output reg[`RegisterBus]         wb_hi,
	output reg[`RegisterBus]         wb_lo,
	output reg						 wb_hilo_we,
	output reg[`RegisterAddressBus]  wb_wd,
	output reg                       wb_wreg,
	output reg[`RegisterBus]         wb_wdata
);

    always @ (posedge clock) begin
	    if (reset == `ResetEnable) begin
		    wb_wd <= `NOPRegisterAddress;
			wb_wreg <= `WriteDisable;
			wb_wdata <= `ZeroWord;
			wb_hi <= `ZeroWord;
			wb_lo <= `ZeroWord;
			wb_hilo_we <= `WriteDisable;
		end else if(stall[4] == 1'b1 && stall[5] == 1'b0) begin
			wb_wd <= `NOPRegisterAddress;
			wb_wreg <= `WriteDisable;
			wb_wdata <= `ZeroWord;
			wb_hi <= `ZeroWord;
			wb_lo <= `ZeroWord;
			wb_hilo_we <= `WriteDisable;
		end else if(stall[4] == 1'b0) begin
		    wb_wd <= mem_wd;
			wb_wreg <= mem_wreg;
			wb_wdata <= mem_wdata;
			wb_hi <= mem_hi;
			wb_lo <= mem_lo;
			wb_hilo_we <= mem_hilo_we;
		end
	end

endmodule